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CY26049-36
FailSafeTM PacketClockTM Global Communications Clock Generator
Features
* Fully integrated phase-locked loop (PLL) * FailSafe output * PLL driven by a crystal oscillator that is phase aligned with external reference * Output frequencies selectable and/or programmed to standard communication frequencies * Low-jitter, high-accuracy outputs * Commercial and Industrial operation * 3.3V 5% operation * 16-lead TSSOP * When reference is in range, SAFE pin is driven high. * When reference is off, DCXO maintains clock outputs. SAFE pin is low. * DCXO maintains continuous operation should the input reference clock fail * Glitch-free transition simplifies system design * Selectable output clock rates include T1/DS1, E1, T3/DS3, E3, and OC-3. * Works with commonly available, low-cost 18.432-MHz crystal * Zero-ppm error for all output frequencies * Performance guaranteed for applications that require an extended temperature range * Compatible across industry standard design platforms * Industry standard package with 6.4 x 5.0 mm2 footprint and a height profile of just 1.1 mm.
Benefits
* Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components
Logic Block Diagram
external pullable crystal (18.432 MHz) XIN Input reference (typical 8 kHz) ICLK
TM FAILSAFE CONTROL
XOUT
DIGITAL CONTROLLED CRYSTAL OSCILLATOR
PHASE LOCKED LOOP
CLK OUTPUT DIVIDERS CLK/2
FS[3:0] frequency select
8K
SAFE High=ICLK detected
Pin Configuration
CY26049-36 16-pin TSSOP Top View
ICLK 1 8K 2 FS1 3 FS2 4 VDD 5 VSS 6 CLK/2 7 XIN 8 16 NC 15 CLK 14 FS0 13 FS3 12 VDD 11 VSS 10 SAFE 9 XOUT
Cypress Semiconductor Corporation Document #: 38-07415 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised July 16, 2004
CY26049-36
Pin Definitions
Pin Name Pin Number ICLK 8K FS1 FS2 VDD VSS CLK/2 XIN XOUT SAFE VSS VDD FS3 FS0 CLK NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Description Reference Input Clock; 8 kHz or 10 to 60 MHz. Clock Output; 8 kHz or high impedance in buffer mode. Frequency Select 1; Determines CLK outputs per Table 1. Frequency Select 2; Determines CLK outputs per Table 1. Voltage Supply; 3.3V. Ground Clock Output; Frequency per Table 1. Pullable Crystal Input; 18.432 MHz. Pullable Crystal Output; 18.432 MHz. High = reference ICLK within range, Low = reference ICLK out of range. Ground Voltage Supply; 3.3V. Frequency Select 3; Determines CLK outputs per Table 1. Frequency Select 0; Determines CLK outputs per Table 1. Clock Output; Frequency per Table 1. No Connect
Selector Guide
Part Number CY26049-36 Input Frequency Range 8 kHz or 10 to 60 MHz Reference Input Crystal: 18.432-MHz pullable Crystal per Cypress Specification Outputs 3 Output Frequencies 8 kHz to 155.52 MHz Selectable (see Table 1)
Functional Description
CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO which serves as a primary clock source. The FailSafe control circuit synchronizes the DCXO with the reference as long as the reference is within the pull range of the crystal. In the event of a reference clock failure the DCXO maintains the last frequency and phase information of the reference clock. The unique feature of the CY26049-36 is that the DCXO
is in fact the primary clocking source. When the reference clock is restored, the DCXO automatically re-synchronizes to the reference. The status of the reference clock input, as detected by the CY26049-36, is reported by the SAFE pin. In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36 can be used as a jitter attenuator. In this mode, extensive jitter on the input clock will be "filtered", resulting in a low-jitter output clock.
Document #: 38-07415 Rev. *C
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CY26049-36
Frequency Select Tables
Table 1. CY26049-36 Frequency Select-Output Decoding Table-External Mode (MHz except as noted) ICLK 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK/2 1.544 2.048 22.368 17.184 77.76 16.384 14.352 High Z[1] 18.528 12.352 7.68 High Z[1] 12.288 16.384 CLK 3.088 4.096 44.736 34.368 155.52 32.768 28.704 High Z[1] 37.056 24.704 15.36 High Z[1] 24.576 32.768 8K 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz High Z[1] 8 kHz 8 kHz 8 kHz High Z[1] 8 kHz 8 kHz Crystal 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432 18.432
Table 2. CY26049-36 Frequency Select-Output Decoding Table-Buffer Mode ICLK 20 to 60 10 to 30 FS3 1 1 FS2 1 1 FS1 1 1 FS0 0 1 CLK/2 ICLK/2 2*ICLK CLK ICLK 4*ICLK 8K High Z[1] High Z[1] Crystal ICLK/2 ICLK
Note: 1. High Z = high impedance.
Document #: 38-07415 Rev. *C
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CY26049-36
Absolute Maximum Conditions
Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage........................................ -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) .... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj=125C...................................>10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V (Above which the useful life may be impaired. For user guidelines, not tested.
Recommended Pullable Crystal Specifications[2]
Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min. - - - 3 - 400 - - 180 14.4 Typ. 18.432 14 - - 0.5 - - - - 18 Max. - - 25 - 2 - -200 7 250 21.6 fF mW ppm ppm pF Units MHz pF
Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance
Recommended Operating Conditions
Parameter VDD TAC TAI CLOAD tpu tER(I) Operating Voltage Ambient Temperature (Commercial Temperature) Ambient Temperature (Industrial Temperature) Max Output Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 8 kHz Input Edge Rate, 20% to 80% of VDD = 3.3V Description Min. 3.15 0 -40 - 0.05 0.07 Typ. 3.3 - - - - - Max. 3.45 70 85 15 500 - Unit V C C pF ms V/ns
DC Electrical Specifications (Commercial Temp: 0 to 70C)
Parameter IOH IOL VIH VIL IIH IIL CIN IOZ IDD Description Output High Current Output Low Current Input High Voltage Input High Voltage Input High Current Input Low Current Input Capacitance Output Leakage Current Supply Current High Z[1] output CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 0100 Test Conditions VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) CMOS Levels CMOS Levels VIH=VDD VIL=0V Min. 12 12 0.7 - - - - - - - Typ. 24 24 - - 5 5 - 5 - - Max. - - - 0.3 10 10 7 - 45 30 Unit mA mA VDD VDD A A pF A mA mA
CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 1101 Note: 2. Ecliptek ECX-5761-18.432 M and ECX-5762-18.432 M meets these specifications.
Document #: 38-07415 Rev. *C
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CY26049-36
DC Electrical Specifications (Industrial Temp: -40 to 85C)
Parameter IOH IOL VIH VIL IIH IIL CIN IOZ IDD Description Output High Current Output Low Current Input High Voltage Input High Voltage Input High Current Input Low Current Input Capacitance Output Leakage Current Supply Current High Z[1] output CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 0100 CLOAD = 15 pF, VDD = 3.45V, FS [3:0] = 1101 Test Conditions VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) CMOS Levels CMOS Levels VIH = VDD VIL = 0V Min. 10 10 0.7 - - - - - - - Typ. 20 20 - - 5 5 - 5 - - Max. - - - 0.3 10 10 7 - 50 35 Unit mA mA VDD VDD A A pF A mA mA
AC Electrical Specifications (Commercial Temp: 0 to 70 C and Industrial Temp: -40 to 85C)
Parameter fICLK-E fICLK-B LR DC = t2/t1 TPJIT1 TPJIT2 t6 tfs_lock ferror ER EF Description Frequency, Input Clock Frequency, Input Clock FailSafe Lock Range[3] Output Duty Cycle Test Conditions Input Clock Frequency, External Mode Input Clock Frequency, Buffer Mode Range of reference ICLK for Safe = High Duty Cycle defined in Figure 1, measured at 50% of VDD RMS Period Jitter, RMS Clock Jitter; output <5 MHz Period Jitter, Peak to Peak, 10,000 periods RMS Period Jitter, RMS PLL Lock Time Failsafe Lock Time Frequency Synthesis Error Rising Edge Rate Falling Edge Rate Time for PLL to lock within 150 ppm of target frequency Time for PLL to lock to ICKL (outputs phase aligned with ICKL and Safe = High) Actual mean frequency error vs. target Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. Min. - 10 -250 45 - - - - - - - 0.8 0.8 Typ. 8.00 - - 50 - - - - - - 0 1.4 1.4 Max. Unit - 60 55 250 50 500 100 3 7 - 2 2 kHz MHz % ps ps ps ps ms s ppm V/ns V/ns
+250 ppm
Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods
Voltage and Timing Definitions
t1 t2 CLK 50% 50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3 80% CLK 20% t4
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Note: 3. Dependent on crystals chosen and crystal specs.
Document #: 38-07415 Rev. *C
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CY26049-36
Test Circuit
ICLK 8K
CLOAD
3 4 14 13 12 11 10 9 1 2 16 15
CLK
CLOAD
VDD
0.1uF
5 6
VDD
0.1uF
CLK/2
CLOAD
7 8
18.432 MHz
Ordering Information
Ordering Code CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 CY26049ZI-36T Lead Free CY26049ZXC-36 CY26049ZXC-36T CY26049ZXI-36 CY26049ZXI-36T Package Type 16-lead TSSOP 16-lead TSSOP-Tape and Reel 16-lead TSSOP 16-lead TSSOP-Tape and Reel 16-lead TSSOP 16-lead TSSOP-Tape and Reel 16-lead TSSOP 16-lead TSSOP-Tape and Reel Operating Temperature Range Commercial 0 to 70C Commercial 0 to 70C Industrial -40 to 85C Industrial -40 to 85C Commercial 0 to 70C Commercial 0 to 70C Industrial -40 to 85C Industrial -40 to 85C
Package Diagram
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07415 Rev. *C Page 6 of 7
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY26049-36
Document History Page
Document Title: CY26049-36 FailSafeTM PacketClockTM Global Communications Clock Generator Document Number: 38-07415 REV. ** *A *B ECN NO. Issue Date 114749 120067 128000 08/08/02 01/06/03 07/15/03 Orig. of Change CKN CKN IJA New Data Sheet Changed "FailSafe is a trademark of Silicon Graphics, Inc." to read "FailSafe is a trademark of Cypress Semiconductor" Changed Benefits to read "When reference is in range, SAFE pin is driven high" Changed first sentence to "CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs" Changed title from "Failsafe PacketClock Global Communications Clocks" to "FailSafe PacketClock Global Communications Clock Generator" Changed definitions in Pin Description Table Replaced format for Absolute Maximum Conditions Replaced Recommended Pullable Crystal Specifications table Added tpu to Recommended Operating Conditions Added IIH and IIL to DC Electrical Specifications Replaced AC Electrical Specifications from Cy26049-16 data sheet Changed Voltage and Timing Definitions to match CY2410 data sheet Moved Package Diagram to end of data sheet Spec. (tER(I)) Input Edge Rate in the Recommended Operating Conditions Table Added Lead Free Devices Description of Change
*C
244412
See ECN
RGL
Document #: 38-07415 Rev. *C
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